Next-generation fiber-optic communications links are being designed to operate at speeds as high as 40 or even 100 gigabits per second. Low-speed digital electronic data streams or “lanes” are combined into a high-speed data stream which is sent to an optical modulator to take advantage of the extremely high data rates that are possible with fiber optics.
Low-speed lanes originating from field programmable gate arrays (FPGA) or application specific integrated circuits (ASIC) often have unknown delays between lanes. These delays can change over a power cycle or when a chip's clock is reset. The delays must be removed (“deskewed”) for proper operation of a high-speed data system. Skew between low-speed lanes in a serializer/deserializer (SERDES) leads to incorrect ordering of data in the output of a multiplexer, for example.
Thus what are needed are systems and methods to resolve skew in low-speed lanes at the input to a MUX as easily as possible.